1. Field of the Invention
This invention relates generally to the field of electronic packaging of printed wiring boards. More particularly, it relates to the fabrication of electronic systems for panel and chip carrier configurations.
2. Discussion of Related Art
The constantly increasing speed of chips is driving increased circuit density on the associated electronic packages for both panel and chip carrier applications. One method to increase packaging density and limit the number of package layers in the Z direction is utilization of stacked vias. Conventional stacked vias contain surface metal lands and the vias are not completely filled. Accordingly, their use in contact with a ground or power plane is somewhat limited. Other drawbacks are that they often utilize more than one metal, such as copper applied by electroless plating, sputter coating or vapor deposition followed by electrolytic copper. The plating of the electroless layer typically requires a seed layer to initiate plating, thereby introducing an additional material. This, as well as the differences in the physical characteristics between the different deposited layers creates an interface between the layers, thereby adversely affecting the conductivity through the interface. Furthermore, the process for forming the vias involves the plating of metal into the vias at the same time as the metal is deposited on the planar surface. This then requires the subsequent removal of the plated metal from the surface.
There is no stacked via structure containing filled landless vias for power or ground connections being used at the present time in electronic packages. There are examples of stacked filled vias having lands. These examples utilize methods that result in plating of the via side wall and bottom surface simultaneously and can result in voided volumes within the plated via. In addition, with traditional seed and plate processes, one cannot be assured that the metal contact at the base of the via is electrically continuous and reliable due to the presence of an additional material interface.